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Commit 22995d1d authored by Hachemin Pierre-Yves's avatar Hachemin Pierre-Yves

IT IS WORKING

parent faaff41a
set_property IOSTANDARD LVCMOS33 [get_ports {switchs[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switchs[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switchs[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switchs[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switchs[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switchs[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switchs[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switchs[0]}]
set_property PACKAGE_PIN Y9 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports output]
set_property IOSTANDARD LVCMOS33 [get_ports sendBtn]
set_property PACKAGE_PIN W12 [get_ports output]
set_property PACKAGE_PIN R16 [get_ports sendBtn]
set_property PACKAGE_PIN M15 [get_ports {switchs[7]}]
set_property PACKAGE_PIN H17 [get_ports {switchs[6]}]
set_property PACKAGE_PIN H18 [get_ports {switchs[5]}]
set_property PACKAGE_PIN H19 [get_ports {switchs[4]}]
set_property PACKAGE_PIN F21 [get_ports {switchs[3]}]
set_property PACKAGE_PIN H22 [get_ports {switchs[2]}]
set_property PACKAGE_PIN G22 [get_ports {switchs[1]}]
set_property PACKAGE_PIN F22 [get_ports {switchs[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sendBtn]
\ No newline at end of file
set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switches[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switches[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switches[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switches[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switches[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switches[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switches[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switches[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports Btn_gobo]
set_property IOSTANDARD LVCMOS33 [get_ports Btn_color]
set_property IOSTANDARD LVCMOS33 [get_ports Btn_pan]
set_property IOSTANDARD LVCMOS33 [get_ports Btn_tilt]
set_property IOSTANDARD LVCMOS33 [get_ports Btn_shutter]
set_property PACKAGE_PIN U14 [get_ports {LED[7]}]
set_property PACKAGE_PIN U19 [get_ports {LED[6]}]
set_property PACKAGE_PIN W22 [get_ports {LED[5]}]
set_property PACKAGE_PIN V22 [get_ports {LED[4]}]
set_property PACKAGE_PIN U21 [get_ports {LED[3]}]
set_property PACKAGE_PIN U22 [get_ports {LED[2]}]
set_property PACKAGE_PIN T21 [get_ports {LED[1]}]
set_property PACKAGE_PIN T22 [get_ports {LED[0]}]
set_property PACKAGE_PIN M15 [get_ports {switches[7]}]
set_property PACKAGE_PIN H17 [get_ports {switches[6]}]
set_property PACKAGE_PIN H18 [get_ports {switches[5]}]
set_property PACKAGE_PIN H19 [get_ports {switches[4]}]
set_property PACKAGE_PIN F21 [get_ports {switches[3]}]
set_property PACKAGE_PIN H22 [get_ports {switches[2]}]
set_property PACKAGE_PIN G22 [get_ports {switches[1]}]
set_property PACKAGE_PIN F22 [get_ports {switches[0]}]
set_property PACKAGE_PIN N15 [get_ports Btn_color]
set_property PACKAGE_PIN T18 [get_ports Btn_gobo]
set_property PACKAGE_PIN P16 [get_ports Btn_pan]
set_property PACKAGE_PIN R16 [get_ports Btn_shutter]
set_property PACKAGE_PIN R18 [get_ports Btn_tilt]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BoardControllerNew is
Port (
switches : in STD_LOGIC_VECTOR (7 downto 0);
Btn_gobo : in STD_LOGIC;
Btn_color : in STD_LOGIC;
Btn_shutter : in STD_LOGIC;
Btn_pan : in STD_LOGIC;
Btn_tilt : in STD_LOGIC;
clk : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR(7 downto 0);
output : out STD_LOGIC
);
end BoardControllerNew;
architecture Behavioral of BoardControllerNew is
signal goboRot1 : STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal goboWheel1 : STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal color1 : STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal shutter1 : STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal pan1 : STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal tilt1 : STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal address : STD_LOGIC_VECTOR (8 downto 0):="000000001";
signal done : STD_LOGIC;
signal goboRot8 : STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal goboWheel4 : STD_LOGIC_VECTOR (3 downto 0):="0000";
signal color4 : STD_LOGIC_VECTOR (3 downto 0):="0000";
signal shutter8 : STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal pan8 : STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal tilt8 : STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal trig_goboRot : STD_LOGIC:='0';
signal trig_goboWheel : STD_LOGIC:='0';
signal trig_color : STD_LOGIC:='0';
signal trig_shutter : STD_LOGIC:='0';
signal trig_pan : STD_LOGIC:='0';
signal trig_tilt : STD_LOGIC:='0';
COMPONENT Int_GoboRot is
Port (
clk : in STD_LOGIC;
trig_goboRot : in STD_LOGIC;
goboRot8 : in STD_LOGIC_VECTOR (7 downto 0);
goboRot : out STD_LOGIC_VECTOR (7 downto 0));
END COMPONENT;
COMPONENT Int_GoboWheel is
Port (
clk : in STD_LOGIC;
trig_goboWheel : in STD_LOGIC;
goboWheel4 : in STD_LOGIC_VECTOR (3 downto 0);
goboWheel : out STD_LOGIC_VECTOR (7 downto 0));
END COMPONENT;
COMPONENT Int_Color is
Port (
clk : in STD_LOGIC;
trig_color : in STD_LOGIC;
color4 : in STD_LOGIC_VECTOR (3 downto 0);
color : out STD_LOGIC_VECTOR (7 downto 0));
END COMPONENT;
COMPONENT Int_Shutter is
Port (
clk : in STD_LOGIC;
trig_shutter : in STD_LOGIC;
shutter8 : in STD_LOGIC_VECTOR (7 downto 0);
shutter : out STD_LOGIC_VECTOR (7 downto 0));
END COMPONENT;
COMPONENT Int_Pan is
Port (
clk : in STD_LOGIC;
trig_pan : in STD_LOGIC;
pan8 : in STD_LOGIC_VECTOR (7 downto 0);
pan : out STD_LOGIC_VECTOR (7 downto 0));
END COMPONENT;
COMPONENT Int_Tilt is
Port (
clk : in STD_LOGIC;
trig_tilt : in STD_LOGIC;
tilt8 : in STD_LOGIC_VECTOR (7 downto 0);
tilt : out STD_LOGIC_VECTOR (7 downto 0));
END COMPONENT;
COMPONENT frameController
Port (
goboWheel : in STD_LOGIC_VECTOR (7 downto 0);
goboRot : in STD_LOGIC_VECTOR (7 downto 0);
color : in STD_LOGIC_VECTOR (7 downto 0);
shutter : in STD_LOGIC_VECTOR (7 downto 0);
pan : in STD_LOGIC_VECTOR (7 downto 0);
tilt : in STD_LOGIC_VECTOR (7 downto 0);
address : in STD_LOGIC_VECTOR (8 downto 0);
send : in STD_LOGIC;
clk : in STD_LOGIC;
tx : out STD_LOGIC;
done : out STD_LOGIC
);
END COMPONENT;
begin
LED <= switches;
GoboRot : Int_GoboRot PORT MAP(
clk => clk,
trig_goboRot => trig_goboRot,
goboRot8 => goboRot8,
goboRot => goboRot1
);
GobotWheel : Int_GoboWheel PORT MAP(
clk => clk,
trig_goboWheel => trig_goboWheel,
goboWheel4 => goboWheel4,
goboWheel => goboWheel1
);
Color : Int_Color PORT MAP(
clk => clk,
trig_color => trig_color,
color4 => color4,
color => color1
);
Shutter : Int_Shutter PORT MAP(
clk => clk,
trig_shutter => trig_shutter,
shutter8 => shutter8,
shutter => shutter1
);
Pan : Int_Pan PORT MAP(
clk => clk,
trig_pan => trig_pan,
pan8 => pan8,
pan => pan1
);
Tilt : Int_Tilt PORT MAP(
clk => clk,
trig_tilt => trig_tilt,
tilt8 => tilt8,
tilt => tilt1
);
FrameGenerator : frameController PORT MAP(
goboWheel => goboWheel1,
goboRot => goboRot1,
color => color1,
shutter => shutter1,
pan => pan1,
tilt => tilt1,
address => address,
send => '1',
clk => clk,
tx => output,
done => done
);
Stim : process(clk)
begin
if clk'event and clk='1' then
if Btn_gobo='1' then
goboRot8 <= switches;
trig_goboRot <= '1';
goboWheel4 <= switches (3 downto 0);
trig_goboWheel <= '1';
elsif Btn_color='1' then
color4 <= switches (3 downto 0);
trig_color <= '1';
elsif Btn_shutter='1' then
shutter8 <= switches;
trig_shutter <= '1';
elsif Btn_pan='1' then
pan8 <= switches;
trig_pan <= '1';
elsif Btn_tilt='1' then
tilt8 <= switches;
trig_tilt <= '1';
else
trig_goboRot <= '0';
trig_goboWheel <= '0';
trig_color <= '0';
trig_shutter <= '0';
trig_pan <= '0';
trig_tilt <= '0';
end if;
end if;
end process;
end Behavioral;
......@@ -10,7 +10,7 @@ entity Int_Address is
end Int_Address;
architecture Behavioral of Int_Address is
signal mem_address : STD_LOGIC_VECTOR(8 downto 0) := "00000001";
signal mem_address : STD_LOGIC_VECTOR(8 downto 0) := "000000001";
begin
address <=mem_address;
memory : process(trig_address)
......
......@@ -10,7 +10,7 @@ entity Int_Pan is
end Int_Pan;
architecture Behavioral of Int_Pan is
signal mem_pan : STD_LOGIC_VECTOR(8 downto 0) := "00000000";
signal mem_pan : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
begin
pan <=mem_pan;
memory : process(trig_pan)
......
......@@ -10,7 +10,7 @@ entity Int_Shutter is
end Int_Shutter;
architecture Behavioral of Int_Shutter is
signal mem_shutter : STD_LOGIC_VECTOR(8 downto 0) := "00000000";
signal mem_shutter : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
begin
shutter <=mem_shutter;
memory : process(trig_shutter)
......
......@@ -10,7 +10,7 @@ entity Int_Tilt is
end Int_Tilt;
architecture Behavioral of Int_Tilt is
signal mem_tilt : STD_LOGIC_VECTOR(8 downto 0) := "00000000";
signal mem_tilt : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
begin
tilt <=mem_tilt;
memory : process(trig_tilt)
......
......@@ -70,12 +70,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Int_Address.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Int_Color.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
......@@ -112,50 +106,68 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/RxFSM.vhd">
<File Path="$PSRCDIR/sources_1/new/clockGenerator.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/RxOverlayer.vhd">
<File Path="$PSRCDIR/sources_1/new/frameController.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/RxSystem.vhd">
<File Path="$PSRCDIR/sources_1/new/frameFSM.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/UART.vhd">
<File Path="$PSRCDIR/sources_1/new/BoardControllerNew.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/clockGenerator.vhd">
<File Path="$PSRCDIR/sources_1/new/Int_Address.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/frameController.vhd">
<File Path="$PSRCDIR/sources_1/new/RxFSM.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/frameFSM.vhd">
<File Path="$PSRCDIR/sources_1/new/RxOverlayer.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/RxSystem.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/UART.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Main.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
......@@ -204,7 +216,7 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="Main"/>
<Option Name="TopModule" Val="BoardControllerNew"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
......@@ -256,21 +268,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/TB_global_file_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/TB_ByteX_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/TB_Sandbox_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/TB_int_color_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
......@@ -321,7 +318,7 @@
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
<Step Id="init_design"/>
......@@ -334,6 +331,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
......
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