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Commit 3af1564a authored by Hachemin Pierre-Yves's avatar Hachemin Pierre-Yves

Serial 2.0

parent 9632e55a
......@@ -16,7 +16,7 @@ signal RxInt : STD_LOGIC;
signal RxSig : STD_LOGIC :='1';
signal TxSig : STD_LOGIC;
signal DataRdy : STD_LOGIC;
Component UART is
component UART is
Port(Send : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR(7 downto 0);
DataOut : out STD_LOGIC_VECTOR(7 downto 0);
......@@ -27,19 +27,18 @@ Component UART is
Clk : in STD_LOGIC);
end component;
begin
SERIAL : UART port map(
Send => '0',
DataIn => "00000000",
DataOut => Data,
RxInt => RxInt,
Rx => RxSig,
Tx => TxSig,
Done => DataRdy,
Clk => Clk
);
FSMTransition : process(Clk)
begin
SERIAL : UART PORT MAP(
Send => '0',
DataIn => "00000000",
DataOut => Data,
RxInt => RxInt,
Rx => RxSig,
Tx => TxSig,
Done => DataRdy,
Clk => Clk
);
begin
if Clk'event and Clk = '1' then
CASE state IS
WHEN Idle =>
......
......@@ -12,10 +12,10 @@ entity RxSystem is
end RxSystem;
architecture Behavioral of RxSystem is
COMPONENT ClockGenerator
COMPONENT clockGenerator
PORT(
MAINCLK : IN std_logic;
TRIGGER : IN std_logic;
ENABLED : IN std_logic;
BAUDRATE : IN INTEGER;
CLKOUT : OUT std_logic
);
......@@ -49,7 +49,7 @@ begin
ClkGen : ClockGenerator PORT MAP(
MAINCLK => Clk,
TRIGGER => BdClkEn,
ENABLED => BdClkEn,
BAUDRATE => BaudRate,
CLKOUT => BdClkO
);
......
......@@ -13,14 +13,14 @@ entity UART is
end UART;
architecture Behavioral of UART is
COMPONENT TxSystem
PORT(
Send : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR(7 downto 0);
Done : out STD_LOGIC;
Clk : in STD_LOGIC;
Tx : out STD_LOGIC);
END COMPONENT;
-- COMPONENT TxSystem
-- PORT(
-- Send : in STD_LOGIC;
-- Data : in STD_LOGIC_VECTOR(7 downto 0);
-- Done : out STD_LOGIC;
-- Clk : in STD_LOGIC;
-- Tx : out STD_LOGIC);
-- END COMPONENT;
COMPONENT RxSystem is
Port(
......@@ -41,13 +41,13 @@ begin
Tx <= TxSig;
RxSig <= Rx;
Tx1 : TxSystem PORT MAP(
Clk => Clk,
Send => Send,
Data => DataIn,
Done => done2,
Tx => TxSig
);
-- Tx1 : TxSystem PORT MAP(
-- Clk => Clk,
-- Send => Send,
-- Data => DataIn,
-- Done => done2,
-- Tx => TxSig
-- );
Rx1 : RxSystem PORT MAP(
Clk => Clk,
......
......@@ -130,44 +130,46 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/TxFSM.vhd">
<File Path="$PSRCDIR/sources_1/new/UART.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/TxSystem.vhd">
<File Path="$PSRCDIR/sources_1/new/clockGenerator.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/UART.vhd">
<File Path="$PSRCDIR/sources_1/new/frameController.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/clockGenerator.vhd">
<File Path="$PSRCDIR/sources_1/new/frameFSM.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/frameController.vhd">
<File Path="$PSRCDIR/sources_1/new/Main.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/frameFSM.vhd">
<File Path="$PSRCDIR/sources_1/new/TxFSM.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Main.vhd">
<File Path="$PSRCDIR/sources_1/new/TxSystem.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
......
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