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Commit 46d7a100 authored by Antoine's avatar Antoine

Trying to change stuff

parent c9c94838
......@@ -2,4 +2,5 @@ LyreTests.cache/
LyreTests.ip_user_files/
LyreTests.sim
LyreTests.runs
LyreTests.hw
*.wcfg
......@@ -136,7 +136,7 @@ begin
WHEN Stop0 =>
TxBx <= '1';
DoneBx <= '0';
WHEN Stop0 =>
WHEN Stop1 =>
TxBx <= '1';
DoneBx <= '0';
END CASE;
......
......@@ -5,7 +5,7 @@ use IEEE.STD_LOGIC_1164.ALL;
entity clockGenerator is
Port (
MAINCLK : in STD_LOGIC;
TRIGGER : in STD_LOGIC;
ENABLED : in STD_LOGIC;
BAUDRATE : in integer;
CLKOUT : out STD_LOGIC
);
......@@ -16,11 +16,11 @@ constant MAINFREQ : integer := 100000000;
signal counter : integer;
begin
process(MAINCLK,TRIGGER)
process(MAINCLK,ENABLED)
begin
If MAINCLK'event and MAINCLK='1' then
if TRIGGER = '1' then
if ENABLED = '1' then
if counter>=MAINFREQ/BAUDRATE then counter<=0;
CLKOUT<='1';
else counter<=counter+1;
......
......@@ -33,7 +33,7 @@
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSABoardId" Val="zed"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTXSimLaunchSim" Val="9"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
......@@ -101,14 +101,27 @@
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/TB_global_file.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/TB_global_file_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="frameController"/>
<Option Name="TopModule" Val="TB_global_file"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/TB_global_file_behav.wcfg"/>
<Option Name="xsim.simulate.runtime" Val="1ms"/>
</Config>
</FileSet>
</FileSets>
......@@ -136,7 +149,9 @@
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
......@@ -144,7 +159,9 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
......
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