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Commit 51ba209a authored by Antoine's avatar Antoine

Mergin

parents 46d7a100 8b5d92d1
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04.02.2018 15:09:08
-- Design Name:
-- Module Name: TB_FSMBreakMAB - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TB_FSMBreakMAB is
-- Port ( );
end TB_FSMBreakMAB;
architecture Behavioral of TB_FSMBreakMAB is
component BreakMABFSM is
Port (
StartBreakMAB : in STD_LOGIC;
BdClk : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkMod : out integer;
TxBreakMAB : out STD_LOGIC;
DoneBreakMAB : out STD_LOGIC);
end component;
component clockGenerator is
Port (
MAINCLK : in STD_LOGIC;
ENABLED : in STD_LOGIC;
BAUDRATE : in integer;
CLKOUT : out STD_LOGIC);
end component;
constant CLK_period : time:= 10ns;
signal StartBreakMAB : STD_LOGIC;
signal BdClk : STD_LOGIC;
signal Clk : STD_LOGIC;
signal ClkMod : integer;
signal TxBreakMAB : STD_LOGIC;
signal DoneBreakMAB : STD_LOGIC;
signal MAINCLK : STD_LOGIC;
signal ENABLED : STD_LOGIC:='1';
signal BAUDRATE : integer:=2500000;
signal CLKOUT : STD_LOGIC;
begin
FSM : BreakMABFSM port map(
StartBreakMAB => StartBreakMAB,
BdClk => CLKOUT,
Clk => Clk,
ClkMod => ClkMod,
TxBreakMAB => TxBreakMAB,
DoneBreakMAB => DoneBreakMAB);
Clock : clockGenerator port map(
MAINCLK => Clk,
ENABLED => ENABLED,
BAUDRATE => BAUDRATE,
CLKOUT => CLKOUT);
-- clock process
CLK_process : process
begin
Clk <= '0';
wait for clk_period/2;
Clk <= '1';
wait for clk_period/2;
end process;
-- stim process
stim_process : process
begin
StartBreakMAB <= '0';
wait for 30ns;
StartBreakMAB <= '1';
wait for 100ns;
StartBreakMAB <= '0';
wait;
end process;
end Behavioral;
......@@ -48,7 +48,7 @@ signal clk : STD_LOGIC;
signal tx : STD_LOGIC;
signal done : STD_LOGIC;
constant CLK_period : time:= 10ns;
constant CLK_period : time:= 1ns;
begin
Frame : frameController port map(
goboWheel => goboWheel,
......
......@@ -14,7 +14,7 @@ end clockGenerator;
architecture Behavioral of clockGenerator is
constant MAINFREQ : integer := 100000000;
signal counter : integer;
signal counter : integer:=0;
begin
process(MAINCLK,ENABLED)
begin
......
......@@ -70,10 +70,10 @@ begin
--clock mode for Break MAB
with ClkMod select BaudRate <=
10000 when 0, --- break
83333 when 1, --- MAB
250000 when 2, --- BX
250000 when others;
10000000 when 0, --- break --10000
8333300 when 1, --- MAB 83333
2500000 when 2, --- BX 250000
2500000 when others; -- 250000
ClkGen : clockGenerator PORT MAP(
MAINCLK => Clk,
......
......@@ -97,7 +97,7 @@ begin
end if;
WHEN Counter =>
if Clk = '1' then
if x <= 512 then -- Slot 0 start code is in it
if x <= 3 then -- Slot 0 start code is in it
state <= ByteX;
else
state <= Idle;
......@@ -138,6 +138,8 @@ begin
x <= x + 1;
end if;
END CASE;
StartBreakMAB <= '0';
StartBX <= '0';
end if;
end process;
......
......@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="35" Path="/data/Softs/Xilinx/Vivado/Projects/LyreTests/LyreTests.xpr">
<Project Version="7" Minor="35" Path="C:/Users/pierr/Documents/PY-ECP/CPSN/PROJET/LaLyre/LaLyre/LyreTests.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="2f8d471511e94bf28fca58a55c77d3c2"/>
......@@ -18,6 +18,7 @@
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="SimulatorLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="em.avnet.com:zed:part0:1.3"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
......@@ -33,7 +34,7 @@
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSABoardId" Val="zed"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="9"/>
<Option Name="WTXSimLaunchSim" Val="20"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
......@@ -107,6 +108,13 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/TB_FSMBreakMAB.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/TB_global_file_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
......@@ -116,7 +124,6 @@
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="TB_global_file"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
......@@ -136,24 +143,22 @@
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
......
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="TB_global_file_behav.wdb" id="1">
<top_modules>
<top_module name="TB_global_file" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="20458402684fs"></ZoomEndTime>
<Cursor1Time time="3364512000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="175"></NameColumnWidth>
<ValueColumnWidth column_width="134"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="18" />
<wvobject type="array" fp_name="/TB_global_file/goboWheel">
<obj_property name="ElementShortName">goboWheel[7:0]</obj_property>
<obj_property name="ObjectShortName">goboWheel[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TB_global_file/goboRot">
<obj_property name="ElementShortName">goboRot[7:0]</obj_property>
<obj_property name="ObjectShortName">goboRot[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TB_global_file/color">
<obj_property name="ElementShortName">color[7:0]</obj_property>
<obj_property name="ObjectShortName">color[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TB_global_file/shutter">
<obj_property name="ElementShortName">shutter[7:0]</obj_property>
<obj_property name="ObjectShortName">shutter[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TB_global_file/pan">
<obj_property name="ElementShortName">pan[7:0]</obj_property>
<obj_property name="ObjectShortName">pan[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TB_global_file/tilt">
<obj_property name="ElementShortName">tilt[7:0]</obj_property>
<obj_property name="ObjectShortName">tilt[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TB_global_file/address">
<obj_property name="ElementShortName">address[8:0]</obj_property>
<obj_property name="ObjectShortName">address[8:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TB_global_file/send">
<obj_property name="ElementShortName">send</obj_property>
<obj_property name="ObjectShortName">send</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TB_global_file/clk">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TB_global_file/tx">
<obj_property name="ElementShortName">tx</obj_property>
<obj_property name="ObjectShortName">tx</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TB_global_file/done">
<obj_property name="ElementShortName">done</obj_property>
<obj_property name="ObjectShortName">done</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TB_global_file/CLK_period">
<obj_property name="ElementShortName">CLK_period</obj_property>
<obj_property name="ObjectShortName">CLK_period</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TB_global_file/Frame/FrameGenerator/state">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
<wvobject fp_name="divider36" type="divider">
<obj_property name="label">BreakMAB</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TB_global_file/Frame/FrameGenerator/FSMBreakMab/state">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
<wvobject fp_name="divider38" type="divider">
<obj_property name="label">ByteX</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="other" fp_name="/TB_global_file/Frame/FrameGenerator/FSMByteX/state">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TB_global_file/Frame/ClkGen/CLKOUT">
<obj_property name="ElementShortName">CLKOUT</obj_property>
<obj_property name="ObjectShortName">CLKOUT</obj_property>
</wvobject>
</wave_config>
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