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Commit 5cc94eb6 authored by Hachemin Pierre-Yves's avatar Hachemin Pierre-Yves

Merge branch 'PY/TB_v2' into 'master'

Py/tb v2

See merge request !3
parents 46d7a100 3185ef5b
......@@ -4,3 +4,4 @@ LyreTests.sim
LyreTests.runs
LyreTests.hw
*.wcfg
*.old
set_property IOSTANDARD LVCMOS33 [get_ports {switchs[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switchs[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switchs[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switchs[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switchs[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switchs[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switchs[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switchs[0]}]
set_property PACKAGE_PIN Y9 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports output]
set_property IOSTANDARD LVCMOS33 [get_ports sendBtn]
set_property PACKAGE_PIN W12 [get_ports output]
set_property PACKAGE_PIN R16 [get_ports sendBtn]
set_property PACKAGE_PIN M15 [get_ports {switchs[7]}]
set_property PACKAGE_PIN H17 [get_ports {switchs[6]}]
set_property PACKAGE_PIN H18 [get_ports {switchs[5]}]
set_property PACKAGE_PIN H19 [get_ports {switchs[4]}]
set_property PACKAGE_PIN F21 [get_ports {switchs[3]}]
set_property PACKAGE_PIN H22 [get_ports {switchs[2]}]
set_property PACKAGE_PIN G22 [get_ports {switchs[1]}]
set_property PACKAGE_PIN F22 [get_ports {switchs[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sendBtn]
\ No newline at end of file
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TB_ByteX is
-- Port ( );
end TB_ByteX;
architecture Behavioral of TB_ByteX is
component ByteXFSM is
Port (
StartBx : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (7 downto 0);
BdClk : in STD_LOGIC;
Clk : in STD_LOGIC;
TxBx : out STD_LOGIC;
DoneBx : out STD_LOGIC);
end component;
component clockGenerator is
Port (
MAINCLK : in STD_LOGIC;
ENABLED : in STD_LOGIC;
BAUDRATE : in integer;
CLKOUT : out STD_LOGIC);
end component;
constant CLK_period : time:= 10ns;
signal StartBx : STD_LOGIC;
signal Data : STD_LOGIC_VECTOR(7 downto 0) := "01100101";
signal BdClk : STD_LOGIC;
signal Clk : STD_LOGIC;
signal ClkMod : integer;
signal TxBx : STD_LOGIC;
signal DoneBx : STD_LOGIC;
signal MAINCLK : STD_LOGIC;
signal ENABLED : STD_LOGIC:='1';
signal BAUDRATE : integer:=2500000;
signal CLKOUT : STD_LOGIC;
begin
FSM : ByteXFSM port map(
StartBx => StartBx,
Data => Data,
BdClk => CLKOUT,
Clk => Clk,
TxBx => TxBx,
DoneBx => DoneBx);
Clock : clockGenerator port map(
MAINCLK => Clk,
ENABLED => ENABLED,
BAUDRATE => BAUDRATE,
CLKOUT => CLKOUT);
-- clock process
CLK_process : process
begin
Clk <= '0';
wait for clk_period/2;
Clk <= '1';
wait for clk_period/2;
end process;
-- stim process
stim_process : process
begin
StartBx <= '0';
wait for 30ns;
StartBx <= '1';
wait for 100ns;
StartBx <= '0';
wait;
end process;
end Behavioral;
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04.02.2018 15:09:08
-- Design Name:
-- Module Name: TB_FSMBreakMAB - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TB_FSMBreakMAB is
-- Port ( );
end TB_FSMBreakMAB;
architecture Behavioral of TB_FSMBreakMAB is
component BreakMABFSM is
Port (
StartBreakMAB : in STD_LOGIC;
BdClk : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkMod : out integer;
TxBreakMAB : out STD_LOGIC;
DoneBreakMAB : out STD_LOGIC);
end component;
component clockGenerator is
Port (
MAINCLK : in STD_LOGIC;
ENABLED : in STD_LOGIC;
BAUDRATE : in integer;
CLKOUT : out STD_LOGIC);
end component;
constant CLK_period : time:= 10ns;
signal StartBreakMAB : STD_LOGIC;
signal BdClk : STD_LOGIC;
signal Clk : STD_LOGIC;
signal ClkMod : integer;
signal TxBreakMAB : STD_LOGIC;
signal DoneBreakMAB : STD_LOGIC;
signal MAINCLK : STD_LOGIC;
signal ENABLED : STD_LOGIC:='1';
signal BAUDRATE : integer:=2500000;
signal CLKOUT : STD_LOGIC;
begin
FSM : BreakMABFSM port map(
StartBreakMAB => StartBreakMAB,
BdClk => CLKOUT,
Clk => Clk,
ClkMod => ClkMod,
TxBreakMAB => TxBreakMAB,
DoneBreakMAB => DoneBreakMAB);
Clock : clockGenerator port map(
MAINCLK => Clk,
ENABLED => ENABLED,
BAUDRATE => BAUDRATE,
CLKOUT => CLKOUT);
-- clock process
CLK_process : process
begin
Clk <= '0';
wait for clk_period/2;
Clk <= '1';
wait for clk_period/2;
end process;
-- stim process
stim_process : process
begin
StartBreakMAB <= '0';
wait for 30ns;
StartBreakMAB <= '1';
wait for 100ns;
StartBreakMAB <= '0';
wait;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TB_Sandbox is
-- Port ( );
end TB_Sandbox;
architecture Behavioral of TB_Sandbox is
component SandBox is
Port (
switchs : in STD_LOGIC_VECTOR (7 downto 0);
sendBtn : in STD_LOGIC;
clk : in STD_LOGIC;
output : out STD_LOGIC
);
end component;
signal switchs : STD_LOGIC_VECTOR (7 downto 0):="00011000";
signal sendBtn : STD_LOGIC;
signal clk : STD_LOGIC;
signal output : STD_LOGIC;
constant CLK_period : time:= 10ns;
begin
Frame : SandBox port map(
switchs => switchs,
sendBtn => sendBtn,
clk => clk,
output => output
);
-- clock process
CLK_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- stim process
stim_process : process
begin
sendBtn <= '0';
wait for 30ns;
sendBtn <= '1';
wait;
end process;
end Behavioral;
......@@ -36,7 +36,7 @@ component frameController is
end component;
signal goboWheel : STD_LOGIC_VECTOR (7 downto 0):="00000001";
signal goboRot : STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal color : STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal color : STD_LOGIC_VECTOR (7 downto 0):="00000100";
signal shutter : STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal pan : STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal tilt : STD_LOGIC_VECTOR (7 downto 0):="00000000";
......@@ -48,7 +48,7 @@ signal clk : STD_LOGIC;
signal tx : STD_LOGIC;
signal done : STD_LOGIC;
constant CLK_period : time:= 10ns;
constant CLK_period : time:= 1ns;
begin
Frame : frameController port map(
goboWheel => goboWheel,
......
......@@ -13,7 +13,7 @@ entity BreakMABFSM is
end BreakMABFSM;
architecture Behavioral of BreakMABFSM is
TYPE STATE_TYPE IS (Idle, Break, MAB);
TYPE STATE_TYPE IS (Idle, Break, MAB, Done);
signal state : STATE_TYPE := Idle;
begin
......@@ -36,10 +36,16 @@ begin
end if;
WHEN MAB =>
if BdClk = '1'then
state <= Idle;
state <= Done;
else
state <= MAB;
end if;
WHEN Done =>
if BdClk = '1' and StartBreakMAB = '0' then
state <= Idle;
else
state <= Done;
end if;
END CASE;
end if;
end process;
......@@ -61,6 +67,10 @@ begin
TxBreakMAB <= '1';
ClkMod <= 1;
DoneBreakMAB <= '0';
WHEN Done =>
TxBreakMAB <= '1';
ClkMod <= 2;
DoneBreakMAB <= '1';
END CASE;
end if;
end process;
......
......@@ -13,7 +13,7 @@ entity ByteXFSM is
end ByteXFSM;
architecture Behavioral of ByteXFSM is
TYPE STATE_TYPE IS (Idle, Start, Tr0, Tr1, Tr2, Tr3, Tr4, Tr5, Tr6, Tr7, Stop0, Stop1);
TYPE STATE_TYPE IS (Idle, Start, Tr0, Tr1, Tr2, Tr3, Tr4, Tr5, Tr6, Tr7, Stop0, Stop1, Done);
signal state : STATE_TYPE := Idle;
begin
......@@ -90,10 +90,16 @@ begin
end if;
WHEN Stop1 =>
if BdClk = '1' then
state <= Idle;
state <= Done;
else
state <= Stop1;
end if;
WHEN Done =>
if BdClk = '1' and StartBX = '0' then
state <= Idle;
else
state <= Done;
end if;
END CASE;
end if;
end process;
......@@ -139,6 +145,9 @@ begin
WHEN Stop1 =>
TxBx <= '1';
DoneBx <= '0';
WHEN Done =>
TxBx <= '1';
DoneBx <= '1';
END CASE;
end if;
end process;
......
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SandBox is
Port (
switchs : in STD_LOGIC_VECTOR (7 downto 0);
sendBtn : in STD_LOGIC;
clk : in STD_LOGIC;
output : out STD_LOGIC
);
end SandBox;
architecture Behavioral of SandBox is
COMPONENT frameController
Port (
goboWheel : in STD_LOGIC_VECTOR (7 downto 0);
goboRot : in STD_LOGIC_VECTOR (7 downto 0);
color : in STD_LOGIC_VECTOR (7 downto 0);
shutter : in STD_LOGIC_VECTOR (7 downto 0);
pan : in STD_LOGIC_VECTOR (7 downto 0);
tilt : in STD_LOGIC_VECTOR (7 downto 0);
address : in STD_LOGIC_VECTOR (8 downto 0);
send : in STD_LOGIC;
clk : in STD_LOGIC;
tx : out STD_LOGIC;
done : out STD_LOGIC
);
END COMPONENT;
signal done : STD_LOGIC;
signal switchMemory : STD_LOGIC_VECTOR (7 downto 0);
signal send : STD_LOGIC := '0';
signal count : integer := 0;
begin
FrameGenerator : frameController PORT MAP(
goboWheel => "00000000",
goboRot => "10111110",
color => "01111000",
shutter => "11001000",
pan => switchs,
tilt => switchs,
address => "000000001",
send => '1',
clk => clk,
tx => output,
done => done
);
end architecture;
......@@ -14,7 +14,7 @@ end clockGenerator;
architecture Behavioral of clockGenerator is
constant MAINFREQ : integer := 100000000;
signal counter : integer;
signal counter : integer:=0;
begin
process(MAINCLK,ENABLED)
begin
......
......@@ -70,10 +70,10 @@ begin
--clock mode for Break MAB
with ClkMod select BaudRate <=
10000 when 0, --- break
83333 when 1, --- MAB
250000 when 2, --- BX
250000 when others;
10000 when 0, --- break --10000
111111 when 1, --- MAB 83333
250000 when 2, --- BX 250000
250000 when others; -- 250000
ClkGen : clockGenerator PORT MAP(
MAINCLK => Clk,
......
......@@ -96,8 +96,8 @@ begin
state <= ByteX;
end if;
WHEN Counter =>
if Clk = '1' then
if x <= 512 then -- Slot 0 start code is in it
if BdClk = '1' then
if x <= 20 then -- Slot 0 start code is in it
state <= ByteX;
else
state <= Idle;
......@@ -124,6 +124,7 @@ begin
StartBX <= '0';
Done <= '0';
BdClkEn <= '1';
x <= 0;
WHEN ByteX =>
StartBreakMAB <= '0';
StartBX <= '1';
......
......@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="35" Path="/data/Softs/Xilinx/Vivado/Projects/LyreTests/LyreTests.xpr">
<Project Version="7" Minor="35" Path="/data/Softs/Xilinx/Vivado/Projects/LaLyre/LyreTests.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="2f8d471511e94bf28fca58a55c77d3c2"/>
......@@ -18,6 +18,7 @@
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="SimulatorLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="em.avnet.com:zed:part0:1.3"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
......@@ -33,7 +34,7 @@
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSABoardId" Val="zed"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="9"/>
<Option Name="WTXSimLaunchSim" Val="59"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
......@@ -75,13 +76,19 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/frameController.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/frameFSM.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/frameController.vhd">
<File Path="$PSRCDIR/sources_1/new/SandBox.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
......@@ -89,20 +96,48 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="frameController"/>
<Option Name="TopModule" Val="SandBox"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/new/IOPORTS1.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/IOPORTS1.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/TB_Sandbox.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/TB_global_file.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/TB_ByteX.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/TB_FSMBreakMAB.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
......@@ -112,16 +147,28 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/TB_ByteX_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/TB_Sandbox_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="TB_global_file"/>
<Option Name="TopModule" Val="TB_Sandbox"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/TB_global_file_behav.wcfg"/>
<Option Name="xsim.simulate.runtime" Val="1ms"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/TB_global_file_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/TB_ByteX_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/TB_Sandbox_behav.wcfg"/>
<Option Name="xsim.simulate.runtime" Val="50ms"/>
</Config>
</FileSet>
</FileSets>
......@@ -147,17 +194,18 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
<Desc>Default settings for Implementation.</Desc>
......@@ -172,6 +220,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
......
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