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Commit 60c349b6 authored by Hachemin Pierre-Yves's avatar Hachemin Pierre-Yves

add all Intermediate blocks, be careful on shutter

parent 5cc94eb6
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Int_Address is
Port (
trig_address : in STD_LOGIC;
address9 : in STD_LOGIC_VECTOR (8 downto 0);
address : out STD_LOGIC_VECTOR (8 downto 0));
end Int_Address;
architecture Behavioral of Int_Address is
signal mem_address : STD_LOGIC_VECTOR(8 downto 0) := "00000001";
begin
address <=mem_address;
memory : process(trig_address)
begin
If trig_address'event and trig_address='1' then
mem_address <= address9;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Int_Color is
Port (
trig_color : in STD_LOGIC;
color4 : in STD_LOGIC_VECTOR (3 downto 0);
color : out STD_LOGIC_VECTOR (7 downto 0));
end Int_Color;
architecture Behavioral of Int_Color is
signal mem_color : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
begin
color <=mem_color;
memory : process(trig_color)
begin
If trig_color'event and trig_color='1' then
CASE color4 IS
WHEN "0000" =>
mem_color <= "00001111"; --15 white
WHEN "0001" =>
mem_color <= "00100011"; --35 red
WHEN "0010" =>
mem_color <= "01000001"; --65 yellow
WHEN "0011" =>
mem_color <= "01011111"; --95 light green
WHEN "0100" =>
mem_color <= "01111101"; --125 pink
WHEN "0101" =>
mem_color <= "10011011"; --155 UV
WHEN "0110" =>
mem_color <= "10011001"; --185 cyan
WHEN "0111" =>
mem_color <= "11001101"; --205 green
WHEN "1000" =>
mem_color <= "00100011"; --235 blue
WHEN "1001" =>
mem_color <= "11111110"; --254 orange
end case;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Int_GoboRot is
Port (
trig_goboRot : in STD_LOGIC;
goboRot8 : in STD_LOGIC_VECTOR (7 downto 0);
goboRot : out STD_LOGIC_VECTOR (7 downto 0));
end Int_GoboRot;
architecture Behavioral of Int_GoboRot is
signal mem_goboRot : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
begin
goboRot <=mem_goboRot;
memory : process(mem_goboRot)
begin
If trig_goboRot'event and trig_goboRot='1' then
mem_goboRot <=goboRot8;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Int_GoboWheel is
Port (
trig_goboWheel : in STD_LOGIC;
goboWheel4 : in STD_LOGIC_VECTOR (3 downto 0);
goboWheel : out STD_LOGIC_VECTOR (7 downto 0));
end Int_GoboWheel;
architecture Behavioral of Int_GoboWheel is
signal mem_goboWheel : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
begin
goboWheel <=mem_goboWheel;
memory : process(trig_goboWheel)
begin
If trig_goboWheel'event and trig_goboWheel='1' then
CASE goboWheel4 IS
WHEN "0000" =>
mem_goboWheel <= "00100000"; --32 open
WHEN "0001" =>
mem_goboWheel <= "01000000"; --64 GOBO 1
WHEN "0010" =>
mem_goboWheel <= "01100000"; --96 GOBO 2
WHEN "0011" =>
mem_goboWheel <= "10000000"; --128 GOBO 3
WHEN "0100" =>
mem_goboWheel <= "10100000"; --160 GOBO 4
WHEN "0101" =>
mem_goboWheel <= "11000000"; --192 GOBO 5
WHEN "0110" =>
mem_goboWheel <= "11100000"; --224 GOBO 6
WHEN "0111" =>
mem_goboWheel <= "11111010"; --250 GOBO 7
end case;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Int_Pan is
Port (
trig_pan : in STD_LOGIC;
pan8 : in STD_LOGIC_VECTOR (7 downto 0);
pan : out STD_LOGIC_VECTOR (7 downto 0));
end Int_Pan;
architecture Behavioral of Int_Pan is
signal mem_pan : STD_LOGIC_VECTOR(8 downto 0) := "00000000";
begin
pan <=mem_pan;
memory : process(trig_pan)
begin
If trig_pan'event and trig_pan='1' then
mem_pan <= pan8;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Int_Shutter is
Port (
trig_shutter : in STD_LOGIC;
shutter7 : in STD_LOGIC_VECTOR (6 downto 0);
shutter : out STD_LOGIC_VECTOR (7 downto 0));
end Int_Shutter;
architecture Behavioral of Int_Shutter is
signal mem_shutter : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
begin
shutter <=mem_shutter;
memory : process(trig_shutter)
begin
If trig_shutter'event and trig_shutter='1' then
CASE shutter7 IS
WHEN "00000000" =>
mem_shutter <= "00000000"; --0 black-out
WHEN "00000001" =>
mem_shutter <= "01000000"; --64 Dimmer
WHEN "00000010" =>
mem_shutter <= "10000000"; --128 Open
--Do not send between 3 and 8 !!
WHEN "00000011" =>
mem_shutter <= "00000000"; --0 black-out
WHEN "00000100" =>
mem_shutter <= "00000000"; --0 black-out
WHEN "00000101" =>
mem_shutter <= "00000000"; --0 black-out
WHEN "00000110" =>
mem_shutter <= "00000000"; --0 black-out
WHEN "00000111" =>
mem_shutter <= "00000000"; --0 black-out
WHEN others =>
mem_shutter <= '1' & shutter7; --translation of 128
end case;
end if;
end process;
end Behavioral;
--8 à 119
\ No newline at end of file
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Int_Tilt is
Port (
trig_tilt : in STD_LOGIC;
tilt8 : in STD_LOGIC_VECTOR (7 downto 0);
tilt : out STD_LOGIC_VECTOR (7 downto 0));
end Int_Tilt;
architecture Behavioral of Int_Tilt is
signal mem_tilt : STD_LOGIC_VECTOR(8 downto 0) := "00000000";
begin
tilt <=mem_tilt;
memory : process(trig_tilt)
begin
If trig_tilt'event and trig_tilt='1' then
mem_tilt <= tilt8;
end if;
end process;
end Behavioral;
......@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="35" Path="/data/Softs/Xilinx/Vivado/Projects/LaLyre/LyreTests.xpr">
<Project Version="7" Minor="35" Path="C:/Users/pierr/Documents/PY-ECP/CPSN/PROJET/LaLyre/LaLyre/LyreTests.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="2f8d471511e94bf28fca58a55c77d3c2"/>
......@@ -94,6 +94,55 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Int_Address.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Int_GoboWheel.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Int_Color.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Int_Tilt.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Int_Shutter.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Int_Pan.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Int_GoboRot.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="SandBox"/>
......@@ -183,33 +232,26 @@
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
......@@ -220,7 +262,6 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
......
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