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Commit 89ade67e authored by Vadot Antoine's avatar Vadot Antoine

Merge branch 'PY/BigFSM' into 'master'

Add Clock mode, BREAKMAB to discuss

See merge request !1
parents 9316fd72 f346d0e2
......@@ -4,7 +4,7 @@ use IEEE.STD_LOGIC_1164.ALL;
entity BreakMABFSM is
Port (
StartBreakMAB : in STD_LOGIC;
BaudClk : in STD_LOGIC;
BdClk : in STD_LOGIC;
Clk : in STD_LOGIC;
TxBreakMAB : out STD_LOGIC;
DoneBreakMAB : out STD_LOGIC);
......
......@@ -7,7 +7,7 @@ entity ByteXFSM is
StartBX : in STD_LOGIC;
Data512 : in STD_LOGIC_VECTOR (4103 downto 0);
IntX : in STD_LOGIC;
BaudClk : in STD_LOGIC;
BdClk : in STD_LOGIC;
Clk : in STD_LOGIC;
TxBX : out STD_LOGIC;
DoneBX : out STD_LOGIC);
......
......@@ -40,13 +40,13 @@ COMPONENT clockGenerator
Tx : OUT std_logic
);
END COMPONENT;
constant BaudRate : integer := 125000;
signal BaudRate : integer := 125000;
signal BdClkEn : std_logic;
signal BdClk : std_logic;
signal data : STD_LOGIC_VECTOR(47 downto 0);
signal data512 : STD_LOGIC_VECTOR(4103 downto 0); -- Init to 0000
signal ClkMod : integer := 3;
begin
......@@ -64,8 +64,14 @@ begin
data(47 downto 40) <= tilt;
-- TOFIX
data512(address+47 downto address) <= data(47 downto 0):
data512(address+47 downto address) <= data(47 downto 0);
--clock mode for Break MAB
with ClkMod select BaudRate <=
9600 when 0,
19200 when 1,
9600 when 2,
6400 when 3,
6400 when others;
ClkGen : clockGenerator PORT MAP(
MAINCLK => Clk,
......
......@@ -15,7 +15,7 @@ entity frameFSM is
end frameFSM;
architecture Behavioral of frameFSM is
TYPE STATE_TYPE IS (Idle, Break, MAB, ByteX, Counter);
TYPE STATE_TYPE IS (Idle, BreakMAB, ByteX, Counter);
shared variable x : integer := 0;
signal state : STATE_TYPE <= Idle;
......@@ -28,21 +28,15 @@ begin
CASE state IS
WHEN Idle =>
if StartTx = '1' then
state <= Break;
state <= BreakMAB;
else
state <= Idle;
end if;
WHEN Break =>
if BdClk = '1' then
state <= MAB;
else
state <= Break;
end if;
WHEN MAB =>
WHEN BreakMAB =>
if BdClk = '1' then
state <= ByteX;
else
state <= MAB;
state <= BreakMAB;
end if;
WHEN ByteX =>
if BdClk = '1' then
......@@ -52,8 +46,7 @@ begin
end if;
WHEN Counter =>
if BdClk = '1' then
if x <= 512 then
if x <= 512 then -- Slot 0 start code is in it
state <= ByteX;
else
state <= Idle;
......@@ -71,18 +64,23 @@ begin
If Clk'event and Clk = '1' then
CASE state IS
WHEN Idle =>
Tx <= '1';
Done <= '1';
BdClkEn <= '0';
ClkMode
WHEN Break =>
Tx <= '0';
Done <= '0';
BdClkEn <= '1';
WHEN ByteX =>
Done <= '0';
BdClkEn <= '1';
StartBreakMAB <= '0';
StartBX <= '0';
Done <= '1';
BdClkEn <= '0';
ClkMode <= 0;
WHEN BreakMAB =>
StartBreakMAB <= '1';
StartBX <= '0';
Done <= '0';
BdClkEn <= '1';
ClkMode <= 1
WHEN ByteX =>
StartBreakMAB <= '0';
StartBX <= '1';
Done <= '0';
BdClkEn <= '1';
ClkMode <= 0;
END CASE;
end if;
end process;
......
......@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="35" Path="/data/Softs/Xilinx/Vivado/Projects/LyreTests/LyreTests.xpr">
<Project Version="7" Minor="35" Path="C:/Users/pierr/Documents/PY-ECP/CPSN/PROJET/LaLyre/LaLyre/LyreTests.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="2f8d471511e94bf28fca58a55c77d3c2"/>
......@@ -57,20 +57,19 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/frameController.vhd">
<File Path="$PSRCDIR/sources_1/new/clockGenerator.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/frameFSM.vhd">
<File Path="$PSRCDIR/sources_1/new/frameController.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/clockGenerator.vhd">
<File Path="$PSRCDIR/sources_1/new/frameFSM.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
......@@ -127,15 +126,12 @@
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
......
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