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Commit 8d6ff610 authored by Vadot Antoine's avatar Vadot Antoine

Merge branch 'PY/intBlocks' into 'master'

Py/int blocks

See merge request !7
parents 5cc94eb6 a2f87a89
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TB_int_color is
-- Port ( );
end TB_int_color;
architecture Behavioral of TB_int_color is
component Int_Color is
Port (
clk : in STD_LOGIC;
trig_color : in STD_LOGIC;
color4 : in STD_LOGIC_VECTOR (3 downto 0);
color : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal color4 : STD_LOGIC_VECTOR (3 downto 0):="0000";
signal trig_color : STD_LOGIC :='0';
signal clk : STD_LOGIC;
signal color : STD_LOGIC_VECTOR (7 downto 0);
constant CLK_period : time:= 10ns;
begin
Frame : Int_Color port map(
clk => clk,
trig_color => trig_color,
color4 => color4,
color => color
);
-- clock process
CLK_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- stim process
stim_process : process
begin
wait for 10ns;
color4 <= "0000";
trig_color <= '1';
wait for 40ns;
trig_color <= '0';
wait for 40ns;
color4 <= "0001";
wait for 40 ns;
trig_color <= '1';
wait for 40ns;
trig_color <= '0';
wait for 40ns;
color4 <= "0011";
wait for 40 ns;
trig_color <= '1';
wait;
wait;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Int_Address is
Port (
clk : in STD_LOGIC;
trig_address : in STD_LOGIC;
address9 : in STD_LOGIC_VECTOR (8 downto 0);
address : out STD_LOGIC_VECTOR (8 downto 0));
end Int_Address;
architecture Behavioral of Int_Address is
signal mem_address : STD_LOGIC_VECTOR(8 downto 0) := "00000001";
begin
address <=mem_address;
memory : process(trig_address)
begin
If clk'event and trig_address='1' then
mem_address <= address9;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Int_Color is
Port (
clk : in STD_LOGIC;
trig_color : in STD_LOGIC;
color4 : in STD_LOGIC_VECTOR (3 downto 0);
color : out STD_LOGIC_VECTOR (7 downto 0));
end Int_Color;
architecture Behavioral of Int_Color is
signal mem_color : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
begin
color <=mem_color;
memory : process(trig_color)
begin
If clk'event and trig_color='1' then
CASE color4 IS
WHEN "0000" =>
mem_color <= "00001111"; --15 white
WHEN "0001" =>
mem_color <= "00100011"; --35 red
WHEN "0010" =>
mem_color <= "01000001"; --65 yellow
WHEN "0011" =>
mem_color <= "01011111"; --95 light green
WHEN "0100" =>
mem_color <= "01111101"; --125 pink
WHEN "0101" =>
mem_color <= "10011011"; --155 UV
WHEN "0110" =>
mem_color <= "10011001"; --185 cyan
WHEN "0111" =>
mem_color <= "11001101"; --205 green
WHEN "1000" =>
mem_color <= "00100011"; --235 blue
WHEN "1001" =>
mem_color <= "11111110"; --254 orange
WHEN others =>
mem_color <= "00000000";
end case;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Int_GoboRot is
Port (
clk : in STD_LOGIC;
trig_goboRot : in STD_LOGIC;
goboRot8 : in STD_LOGIC_VECTOR (7 downto 0);
goboRot : out STD_LOGIC_VECTOR (7 downto 0));
end Int_GoboRot;
architecture Behavioral of Int_GoboRot is
signal mem_goboRot : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
begin
goboRot <=mem_goboRot;
memory : process(mem_goboRot)
begin
If clk'event and trig_goboRot='1' then
mem_goboRot <=goboRot8;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Int_GoboWheel is
Port (
clk : in STD_LOGIC;
trig_goboWheel : in STD_LOGIC;
goboWheel4 : in STD_LOGIC_VECTOR (3 downto 0);
goboWheel : out STD_LOGIC_VECTOR (7 downto 0));
end Int_GoboWheel;
architecture Behavioral of Int_GoboWheel is
signal mem_goboWheel : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
begin
goboWheel <=mem_goboWheel;
memory : process(trig_goboWheel)
begin
If clk'event and trig_goboWheel='1' then
CASE goboWheel4 IS
WHEN "0000" =>
mem_goboWheel <= "00100000"; --32 open
WHEN "0001" =>
mem_goboWheel <= "01000000"; --64 GOBO 1
WHEN "0010" =>
mem_goboWheel <= "01100000"; --96 GOBO 2
WHEN "0011" =>
mem_goboWheel <= "10000000"; --128 GOBO 3
WHEN "0100" =>
mem_goboWheel <= "10100000"; --160 GOBO 4
WHEN "0101" =>
mem_goboWheel <= "11000000"; --192 GOBO 5
WHEN "0110" =>
mem_goboWheel <= "11100000"; --224 GOBO 6
WHEN "0111" =>
mem_goboWheel <= "11111010"; --250 GOBO 7
WHEN others =>
mem_goboWheel <= "00000000";
end case;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Int_Pan is
Port (
clk : in STD_LOGIC;
trig_pan : in STD_LOGIC;
pan8 : in STD_LOGIC_VECTOR (7 downto 0);
pan : out STD_LOGIC_VECTOR (7 downto 0));
end Int_Pan;
architecture Behavioral of Int_Pan is
signal mem_pan : STD_LOGIC_VECTOR(8 downto 0) := "00000000";
begin
pan <=mem_pan;
memory : process(trig_pan)
begin
If clk'event and trig_pan='1' then
mem_pan <= pan8;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Int_Shutter is
Port (
clk : in STD_LOGIC;
trig_shutter : in STD_LOGIC;
shutter8 : in STD_LOGIC_VECTOR (7 downto 0);
shutter : out STD_LOGIC_VECTOR (7 downto 0));
end Int_Shutter;
architecture Behavioral of Int_Shutter is
signal mem_shutter : STD_LOGIC_VECTOR(8 downto 0) := "00000000";
begin
shutter <=mem_shutter;
memory : process(trig_shutter)
begin
If clk'event and trig_shutter='1' then
mem_shutter <= shutter8;
end if;
end process;
end Behavioral;
\ No newline at end of file
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Int_Tilt is
Port (
clk : in STD_LOGIC;
trig_tilt : in STD_LOGIC;
tilt8 : in STD_LOGIC_VECTOR (7 downto 0);
tilt : out STD_LOGIC_VECTOR (7 downto 0));
end Int_Tilt;
architecture Behavioral of Int_Tilt is
signal mem_tilt : STD_LOGIC_VECTOR(8 downto 0) := "00000000";
begin
tilt <=mem_tilt;
memory : process(trig_tilt)
begin
If clk'event and trig_tilt='1' then
mem_tilt <= tilt8;
end if;
end process;
end Behavioral;
......@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="35" Path="/data/Softs/Xilinx/Vivado/Projects/LaLyre/LyreTests.xpr">
<Project Version="7" Minor="35" Path="C:/Users/pierr/Documents/PY-ECP/CPSN/PROJET/LaLyre/LaLyre/LyreTests.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="2f8d471511e94bf28fca58a55c77d3c2"/>
......@@ -34,7 +34,7 @@
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSABoardId" Val="zed"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="59"/>
<Option Name="WTXSimLaunchSim" Val="61"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
......@@ -94,6 +94,62 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Int_Address.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Int_GoboWheel.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Int_Color.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Int_Tilt.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Int_Shutter.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Int_Pan.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/Int_GoboRot.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/BoardController.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="SandBox"/>
......@@ -115,8 +171,15 @@
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/TB_int_color.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/TB_Sandbox.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
......@@ -157,9 +220,14 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/TB_int_color_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="TB_Sandbox"/>
<Option Name="TopModule" Val="TB_int_color"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
......@@ -168,7 +236,8 @@
<Option Name="XSimWcfgFile" Val="$PPRDIR/TB_global_file_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/TB_ByteX_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/TB_Sandbox_behav.wcfg"/>
<Option Name="xsim.simulate.runtime" Val="50ms"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/TB_int_color_behav.wcfg"/>
<Option Name="xsim.simulate.runtime" Val="200 ns"/>
</Config>
</FileSet>
</FileSets>
......@@ -183,15 +252,12 @@
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
......@@ -205,7 +271,7 @@
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
<Desc>Default settings for Implementation.</Desc>
......@@ -220,7 +286,6 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
......
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