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Commit 903eb99e authored by Hachemin Pierre-Yves's avatar Hachemin Pierre-Yves

TB v2

parent eeeb3b05
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04.02.2018 15:09:08
-- Design Name:
-- Module Name: TB_FSMBreakMAB - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TB_FSMBreakMAB is
-- Port ( );
end TB_FSMBreakMAB;
architecture Behavioral of TB_FSMBreakMAB is
component BreakMABFSM is
Port (
StartBreakMAB : in STD_LOGIC;
BdClk : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkMod : out integer;
TxBreakMAB : out STD_LOGIC;
DoneBreakMAB : out STD_LOGIC);
end component;
component clockGenerator is
Port (
MAINCLK : in STD_LOGIC;
ENABLED : in STD_LOGIC;
BAUDRATE : in integer;
CLKOUT : out STD_LOGIC);
end component;
constant CLK_period : time:= 10ns;
signal StartBreakMAB : STD_LOGIC;
signal BdClk : STD_LOGIC;
signal Clk : STD_LOGIC;
signal ClkMod : integer;
signal TxBreakMAB : STD_LOGIC;
signal DoneBreakMAB : STD_LOGIC;
signal MAINCLK : STD_LOGIC;
signal ENABLED : STD_LOGIC:='1';
signal BAUDRATE : integer:=2500000;
signal CLKOUT : STD_LOGIC;
begin
FSM : BreakMABFSM port map(
StartBreakMAB => StartBreakMAB,
BdClk => CLKOUT,
Clk => Clk,
ClkMod => ClkMod,
TxBreakMAB => TxBreakMAB,
DoneBreakMAB => DoneBreakMAB);
Clock : clockGenerator port map(
MAINCLK => Clk,
ENABLED => ENABLED,
BAUDRATE => BAUDRATE,
CLKOUT => CLKOUT);
-- clock process
CLK_process : process
begin
Clk <= '0';
wait for clk_period/2;
Clk <= '1';
wait for clk_period/2;
end process;
-- stim process
stim_process : process
begin
StartBreakMAB <= '0';
wait for 30ns;
StartBreakMAB <= '1';
wait for 100ns;
StartBreakMAB <= '0';
wait;
end process;
end Behavioral;
......@@ -48,7 +48,7 @@ signal clk : STD_LOGIC;
signal tx : STD_LOGIC;
signal done : STD_LOGIC;
constant CLK_period : time:= 10ns;
constant CLK_period : time:= 1ns;
begin
Frame : frameController port map(
goboWheel => goboWheel,
......
......@@ -136,7 +136,7 @@ begin
WHEN Stop0 =>
TxBx <= '1';
DoneBx <= '0';
WHEN Stop0 =>
WHEN Stop1 =>
TxBx <= '1';
DoneBx <= '0';
END CASE;
......
......@@ -5,7 +5,7 @@ use IEEE.STD_LOGIC_1164.ALL;
entity clockGenerator is
Port (
MAINCLK : in STD_LOGIC;
TRIGGER : in STD_LOGIC;
ENABLED : in STD_LOGIC;
BAUDRATE : in integer;
CLKOUT : out STD_LOGIC
);
......@@ -14,14 +14,15 @@ end clockGenerator;
architecture Behavioral of clockGenerator is
constant MAINFREQ : integer := 100000000;
signal counter : integer;
signal counter : integer:=0;
begin
process(MAINCLK,TRIGGER)
process(MAINCLK,ENABLED)
begin
If MAINCLK'event and MAINCLK='1' then
if TRIGGER = '1' then
if counter>=MAINFREQ/BAUDRATE then counter<=0;
if ENABLED = '1' then
if counter>=MAINFREQ/BAUDRATE then
counter<=0;
CLKOUT<='1';
else counter<=counter+1;
CLKOUT<='0';
......
......@@ -70,10 +70,10 @@ begin
--clock mode for Break MAB
with ClkMod select BaudRate <=
10000 when 0, --- break
83333 when 1, --- MAB
250000 when 2, --- BX
250000 when others;
10000000 when 0, --- break --10000
8333300 when 1, --- MAB 83333
2500000 when 2, --- BX 250000
2500000 when others; -- 250000
ClkGen : clockGenerator PORT MAP(
MAINCLK => Clk,
......
......@@ -97,7 +97,7 @@ begin
end if;
WHEN Counter =>
if Clk = '1' then
if x <= 512 then -- Slot 0 start code is in it
if x <= 3 then -- Slot 0 start code is in it
state <= ByteX;
else
state <= Idle;
......@@ -138,6 +138,8 @@ begin
x <= x + 1;
end if;
END CASE;
StartBreakMAB <= '0';
StartBX <= '0';
end if;
end process;
......
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