Ce serveur Gitlab sera éteint le 30 juin 2020, pensez à migrer vos projets vers les serveurs gitlab-research.centralesupelec.fr et gitlab-student.centralesupelec.fr !

Commit 9316fd72 authored by Antoine's avatar Antoine

Defining basic FSM

parent 86fe126a
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BreakMABFSM is
Port (
StartBreakMAB : in STD_LOGIC;
BaudClk : in STD_LOGIC;
Clk : in STD_LOGIC;
TxBreakMAB : out STD_LOGIC;
DoneBreakMAB : out STD_LOGIC);
end BreakMABFSM;
architecture Behavioral of BreakMABFSM is
begin
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ByteXFSM is
Port (
StartBX : in STD_LOGIC;
Data512 : in STD_LOGIC_VECTOR (4103 downto 0);
IntX : in STD_LOGIC;
BaudClk : in STD_LOGIC;
Clk : in STD_LOGIC;
TxBX : out STD_LOGIC;
DoneBX : out STD_LOGIC);
end ByteXFSM;
architecture Behavioral of ByteXFSM is
begin
end Behavioral;
......@@ -79,8 +79,8 @@ begin
Tx <= '0';
Done <= '0';
BdClkEn <= '1';
WHEN Tr0 =>
Tx <= Data(7);
WHEN ByteX =>
Done <= '0';
BdClkEn <= '1';
END CASE;
......
......@@ -77,6 +77,20 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/BreakMABFSM.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/ByteXFSM.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="frameController"/>
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment