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Commit a2f87a89 authored by Hachemin Pierre-Yves's avatar Hachemin Pierre-Yves

add TB int color & 'others' in case

parent 4f6703dc
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TB_int_color is
-- Port ( );
end TB_int_color;
architecture Behavioral of TB_int_color is
component Int_Color is
Port (
clk : in STD_LOGIC;
trig_color : in STD_LOGIC;
color4 : in STD_LOGIC_VECTOR (3 downto 0);
color : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal color4 : STD_LOGIC_VECTOR (3 downto 0):="0000";
signal trig_color : STD_LOGIC :='0';
signal clk : STD_LOGIC;
signal color : STD_LOGIC_VECTOR (7 downto 0);
constant CLK_period : time:= 10ns;
begin
Frame : Int_Color port map(
clk => clk,
trig_color => trig_color,
color4 => color4,
color => color
);
-- clock process
CLK_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- stim process
stim_process : process
begin
wait for 10ns;
color4 <= "0000";
trig_color <= '1';
wait for 40ns;
trig_color <= '0';
wait for 40ns;
color4 <= "0001";
wait for 40 ns;
trig_color <= '1';
wait for 40ns;
trig_color <= '0';
wait for 40ns;
color4 <= "0011";
wait for 40 ns;
trig_color <= '1';
wait;
wait;
end process;
end Behavioral;
......@@ -36,7 +36,9 @@ If clk'event and trig_color='1' then
WHEN "1000" =>
mem_color <= "00100011"; --235 blue
WHEN "1001" =>
mem_color <= "11111110"; --254 orange
mem_color <= "11111110"; --254 orange
WHEN others =>
mem_color <= "00000000";
end case;
end if;
end process;
......
......@@ -32,7 +32,9 @@ begin
WHEN "0110" =>
mem_goboWheel <= "11100000"; --224 GOBO 6
WHEN "0111" =>
mem_goboWheel <= "11111010"; --250 GOBO 7
mem_goboWheel <= "11111010"; --250 GOBO 7
WHEN others =>
mem_goboWheel <= "00000000";
end case;
end if;
end process;
......
......@@ -34,7 +34,7 @@
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSABoardId" Val="zed"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="59"/>
<Option Name="WTXSimLaunchSim" Val="61"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
......@@ -171,8 +171,15 @@
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/TB_int_color.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/TB_Sandbox.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
......@@ -213,9 +220,14 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/TB_int_color_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="TB_Sandbox"/>
<Option Name="TopModule" Val="TB_int_color"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
......@@ -224,7 +236,8 @@
<Option Name="XSimWcfgFile" Val="$PPRDIR/TB_global_file_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/TB_ByteX_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/TB_Sandbox_behav.wcfg"/>
<Option Name="xsim.simulate.runtime" Val="50ms"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/TB_int_color_behav.wcfg"/>
<Option Name="xsim.simulate.runtime" Val="200 ns"/>
</Config>
</FileSet>
</FileSets>
......@@ -249,7 +262,9 @@
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
......@@ -258,7 +273,9 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
......
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