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Commit cb945384 authored by Antoine's avatar Antoine

Cleaning the 3 FSMs

parent 14e8f92c
......@@ -3,16 +3,67 @@ use IEEE.STD_LOGIC_1164.ALL;
entity BreakMABFSM is
Port (
StartBreakMAB : in STD_LOGIC;
BdClk : in STD_LOGIC;
Clk : in STD_LOGIC;
TxBreakMAB : out STD_LOGIC;
DoneBreakMAB : out STD_LOGIC);
StartBreakMAB : in STD_LOGIC;
BdClk : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkMod : out integer;
TxBreakMAB : out STD_LOGIC;
DoneBreakMAB : out STD_LOGIC);
end BreakMABFSM;
architecture Behavioral of BreakMABFSM is
TYPE STATE_TYPE IS (Idle, Break, MAB);
signal state : STATE_TYPE := Idle;
begin
-- Machine d'etat
FSMBreakMabTransition : process(Clk)
begin
If Clk'event and Clk = '1' then
CASE state IS
WHEN Idle =>
if StartBreakMAB = '1' then
state <= Break;
else
state <= Idle;
end if;
WHEN Break =>
if BdClk = '1' then
state <= MAB;
else
state <= Break;
end if;
WHEN MAB =>
if BdClk = '1'then
state <= Idle;
else
state <= MAB;
end if;
END CASE;
end if;
end process;
-- Decodage
FSM1Value : process(Clk)
begin
If Clk'event and Clk = '1' then
CASE state IS
WHEN Idle =>
TxBreakMAB <= '1';
ClkMod <= 2;
DoneBreakMAB <= '1';
WHEN Break =>
TxBreakMAB <= '0';
ClkMod <= 0;
DoneBreakMAB <= '0';
WHEN MAB =>
TxBreakMAB <= '1';
ClkMod <= 1;
DoneBreakMAB <= '0';
END CASE;
end if;
end process;
end Behavioral;
......@@ -4,18 +4,17 @@ use IEEE.STD_LOGIC_1164.ALL;
entity ByteXFSM is
Port (
StartBX : in STD_LOGIC;
Data512 : in STD_LOGIC_VECTOR (4103 downto 0);
IntX : in STD_LOGIC;
StartBx : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (7 downto 0);
BdClk : in STD_LOGIC;
Clk : in STD_LOGIC;
TxBX : out STD_LOGIC;
DoneBX : out STD_LOGIC);
TxBx : out STD_LOGIC;
DoneBx : out STD_LOGIC);
end ByteXFSM;
architecture Behavioral of ByteXFSM is
TYPE STATE_TYPE IS (Idle, Start, Tr0, Tr1, Tr2, Tr3, Tr4, Tr5, Tr6, Tr7, Stop0, Stop1);
signal state : STATE_TYPE <= Idle;
signal state : STATE_TYPE := Idle;
begin
-- Machine d'etat
......@@ -105,53 +104,41 @@ begin
If Clk'event and Clk = '1' then
CASE state IS
WHEN Idle =>
Tx <= '1';
Done <= '1';
BdClkEn <= '0';
TxBx <= '1';
DoneBx <= '1';
WHEN Start =>
Tx <= '0';
Done <= '0';
BdClkEn <= '1';
TxBx <= '0';
DoneBx <= '0';
WHEN Tr0 =>
Tx <= Data(7);
Done <= '0';
BdClkEn <= '1';
TxBx <= Data(0);
DoneBx <= '0';
WHEN Tr1 =>
Tx <= Data(6);
Done <= '0';
BdClkEn <= '1';
TxBx <= Data(1);
DoneBx <= '0';
WHEN Tr2 =>
Tx <= Data(5);
Done <= '0';
BdClkEn <= '1';
TxBx <= Data(2);
DoneBx <= '0';
WHEN Tr3 =>
Tx <= Data(4);
Done <= '0';
BdClkEn <= '1';
TxBx <= Data(3);
DoneBx <= '0';
WHEN Tr4 =>
Tx <= Data(3);
Done <= '0';
BdClkEn <= '1';
TxBx <= Data(4);
DoneBx <= '0';
WHEN Tr5 =>
Tx <= Data(2);
Done <= '0';
BdClkEn <= '1';
TxBx <= Data(5);
DoneBx <= '0';
WHEN Tr6 =>
Tx <= Data(1);
Done <= '0';
BdClkEn <= '1';
TxBx <= Data(6);
DoneBx <= '0';
WHEN Tr7 =>
Tx <= Data(0);
Done <= '0';
BdClkEn <= '1';
TxBx <= Data(7);
DoneBx <= '0';
WHEN Stop0 =>
Tx <= '1';
Done <= '0';
BdClkEn <= '1';
TxBx <= '1';
DoneBx <= '0';
WHEN Stop0 =>
Tx <= '1';
Done <= '0';
BdClkEn <= '1';
TxBx <= '1';
DoneBx <= '0';
END CASE;
end if;
end process;
......
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity frameController is
Port (
goboWheel : in STD_LOGIC_VECTOR (7 downto 0);
goboRot : in STD_LOGIC_VECTOR (7 downto 0);
color : in STD_LOGIC_VECTOR (7 downto 0);
shutter : in STD_LOGIC_VECTOR (7 downto 0);
pan : in STD_LOGIC_VECTOR (7 downto 0);
tilt : in STD_LOGIC_VECTOR (7 downto 0);
address : in STD_LOGIC_VECTOR (8 downto 0);
goboWheel : in STD_LOGIC_VECTOR (7 downto 0);
goboRot : in STD_LOGIC_VECTOR (7 downto 0);
color : in STD_LOGIC_VECTOR (7 downto 0);
shutter : in STD_LOGIC_VECTOR (7 downto 0);
pan : in STD_LOGIC_VECTOR (7 downto 0);
tilt : in STD_LOGIC_VECTOR (7 downto 0);
address : in STD_LOGIC_VECTOR (8 downto 0);
send : in STD_LOGIC;
done: out STD_LOGIC;
send : in STD_LOGIC;
clk : in STD_LOGIC;
clk : in STD_LOGIC;
tx : out STD_LOGIC
tx : out STD_LOGIC;
done : out STD_LOGIC
);
end frameController;
architecture Behavioral of frameController is
COMPONENT clockGenerator
PORT(
MAINCLK : IN std_logic;
TRIGGER : IN std_logic;
BAUDRATE : IN INTEGER;
CLKOUT : OUT std_logic
);
COMPONENT clockGenerator
PORT(
MAINCLK : in std_logic;
ENABLED : in std_logic;
BAUDRATE : in INTEGER;
CLKOUT : out std_logic
);
END COMPONENT;
COMPONENT frameFSM
PORT(
Clk : IN std_logic;
BdClk : IN std_logic;
StartTx : IN std_logic;
Data : in STD_LOGIC_VECTOR(7 downto 0);
Done : OUT std_logic;
BdClkEn : OUT std_logic;
Tx : OUT std_logic
);
PORT(
Clk : in std_logic;
BdClk : in std_logic;
StartTx : in std_logic;
Data512 : in STD_LOGIC_VECTOR(4103 downto 0);
ClkMod : out integer;
Done : out std_logic;
BdClkEn : out std_logic;
TxBreakMAB : out std_logic;
TxBx : out std_logic
);
END COMPONENT;
signal BaudRate : integer := 125000;
signal BaudRate : integer := 250000;
signal BdClkEn : std_logic;
signal BdClk : std_logic;
signal data : STD_LOGIC_VECTOR(47 downto 0);
signal data512 : STD_LOGIC_VECTOR(4103 downto 0); -- Init to 0000
signal ClkMod : integer := 3;
signal data : STD_LOGIC_VECTOR(47 downto 0);
signal data512 : STD_LOGIC_VECTOR(4103 downto 0) := (others => '0'); -- Init to 000000 ... 0000
signal ClkMod : integer := 2;
signal TxBreakMAB : std_logic;
signal TxBx : std_logic;
begin
data(7 downto 0) <= goboWheel;
data(15 downto 8) <= goboRot;
data(23 downto 16) <= color;
data(31 downto 24) <= shutter;
data(39 downto 32) <= pan;
data(47 downto 40) <= tilt;
data512((TO_INTEGER(unsigned(address)) * 8 +47) downto TO_INTEGER(unsigned(address))*8) <= data(47 downto 0);
--- DONT DO THAT => WILL BROKE EVERYTHING
variable ifor : integer := 0;
for ifor in 0 to 4103 loop
data512(ifor) <= '0';
end loop ;
data(7 downto 0) <= goboWheel;
data(15 downto 8) <= goboRot;
data(23 downto 16) <= color;
data(31 downto 24) <= shutter;
data(39 downto 32) <= pan;
data(47 downto 40) <= tilt;
Tx <= TxBreakMAB and TxBx; -- Multiplexing output
-- TOFIX
data512(address+47 downto address) <= data(47 downto 0);
--clock mode for Break MAB
with ClkMod select BaudRate <=
9600 when 0,
19200 when 1,
9600 when 2,
6400 when 3,
6400 when others;
--clock mode for Break MAB
with ClkMod select BaudRate <=
10000 when 0, --- break
83333 when 1, --- MAB
250000 when 2, --- BX
250000 when others;
ClkGen : clockGenerator PORT MAP(
MAINCLK => Clk,
TRIGGER => BdClkEn,
BAUDRATE => BaudRate,
CLKOUT => BdClk
MAINCLK => Clk,
ENABLED => BdClkEn,
BAUDRATE => BaudRate,
CLKOUT => BdClk
);
FrameGenerator : frameFSM PORT MAP(
Clk => Clk,
BdClk => BdClk,
StartTx => Send,
Data => Data,
Done => Done,
BdClkEn => BdClkEn,
Tx => Tx
Clk => Clk,
BdClk => BdClk,
ClkMod => ClkMod,
StartTx => Send,
Data512 => Data512,
Done => Done,
BdClkEn => BdClkEn,
TxBreakMAB => TxBreakMAB,
TxBx => TxBx
);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity frameFSM is
Port(
Clk : in STD_LOGIC;
BdClk : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR(47 downto 0);
StartTx : in STD_LOGIC;
Done : out STD_LOGIC;
BdClkEn : out STD_LOGIC;
Tx : out STD_LOGIC;
ClkMod : out INTEGER range 0 to 3
Clk : in std_logic;
BdClk : in std_logic;
StartTx : in std_logic;
Data512 : in STD_LOGIC_VECTOR(4103 downto 0);
ClkMod : out integer;
Done : out std_logic;
BdClkEn : out std_logic;
TxBreakMAB : out std_logic;
TxBx : out std_logic
);
end frameFSM;
architecture Behavioral of frameFSM is
TYPE STATE_TYPE IS (Idle, BreakMAB, ByteX, Counter);
shared variable x : integer := 0;
signal state : STATE_TYPE <= Idle;
signal x : integer := 0;
signal state : STATE_TYPE := Idle;
signal data : std_logic_vector (7 downto 0) := "00000000";
signal StartBreakMAB : std_logic := '0';
signal StartBx : std_logic := '0';
signal DoneBreakMAB : std_logic := '0';
signal DoneBx : std_logic := '0';
COMPONENT BreakMABFSM
Port (
StartBreakMAB : in STD_LOGIC;
BdClk : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkMod: out integer;
TxBreakMAB : out STD_LOGIC;
DoneBreakMAB : out STD_LOGIC);
END COMPONENT;
COMPONENT ByteXFSM
Port (
StartBx : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (7 downto 0);
BdClk : in STD_LOGIC;
Clk : in STD_LOGIC;
TxBx : out STD_LOGIC;
DoneBx : out STD_LOGIC);
END COMPONENT;
begin
FSMBreakMab : BreakMABFSM PORT MAP(
StartBreakMAB => StartBreakMAB,
BdClk => BdClk,
Clk => Clk,
ClkMod => ClkMod,
TxBreakMAB => TxBreakMAB,
DoneBreakMAB => DoneBreakMAB
);
data <= Data512((x*8+7) downto (x*8));
FSMByteX : ByteXFSM PORT MAP(
StartBx => StartBx,
Data => data,
BdClk => BdClk,
Clk => Clk,
TxBx => TxBx,
DoneBx => DoneBx
);
-- Machine d'etat
FSM1Transition : process(Clk)
begin
......@@ -33,24 +84,24 @@ begin
state <= Idle;
end if;
WHEN BreakMAB =>
if BdClk = '1' then
if BdClk = '1' and DoneBreakMAB = '1' then
state <= ByteX;
else
state <= BreakMAB;
end if;
WHEN ByteX =>
if BdClk = '1' then
if BdClk = '1' and DoneBx = '1' then
state <= Counter;
else
state <= ByteX;
end if;
WHEN Counter =>
if BdClk = '1' then
if x <= 512 then -- Slot 0 start code is in it
if Clk = '1' then
if x <= 512 then -- Slot 0 start code is in it
state <= ByteX;
else
else
state <= Idle;
end if
end if;
else
state <= Counter;
end if;
......@@ -68,19 +119,24 @@ begin
StartBX <= '0';
Done <= '1';
BdClkEn <= '0';
ClkMode <= 0;
WHEN BreakMAB =>
StartBreakMAB <= '1';
StartBX <= '0';
Done <= '0';
BdClkEn <= '1';
ClkMode <= 1
WHEN ByteX =>
StartBreakMAB <= '0';
StartBX <= '1';
Done <= '0';
BdClkEn <= '1';
ClkMode <= 0;
WHEN Counter =>
StartBreakMAB <= '0';
StartBX <= '0';
Done <= '0';
BdClkEn <= '1';
if BdClk = '1' then
x <= x + 1;
end if;
END CASE;
end if;
end process;
......
......@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="35" Path="C:/Users/pierr/Documents/PY-ECP/CPSN/PROJET/LaLyre/LaLyre/LyreTests.xpr">
<Project Version="7" Minor="35" Path="/data/Softs/Xilinx/Vivado/Projects/LyreTests/LyreTests.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="2f8d471511e94bf28fca58a55c77d3c2"/>
......@@ -57,35 +57,32 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/clockGenerator.vhd">
<File Path="$PSRCDIR/sources_1/new/BreakMABFSM.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/frameController.vhd">
<File Path="$PSRCDIR/sources_1/new/ByteXFSM.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/frameFSM.vhd">
<File Path="$PSRCDIR/sources_1/new/clockGenerator.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/BreakMABFSM.vhd">
<File Path="$PSRCDIR/sources_1/new/frameFSM.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/ByteXFSM.vhd">
<File Path="$PSRCDIR/sources_1/new/frameController.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
......@@ -126,12 +123,15 @@
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
......
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